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Vulkan: Restrict feedback loop detection to AMD RDNA 3 GPUs

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See merge request [ryubing/ryujinx!25](https://git.ryujinx.app/ryubing/ryujinx/-/merge_requests/25)
This commit is contained in:
KeatonTheBot 2025-05-13 19:27:24 -05:00 committed by GreemDev
parent 21971a2be7
commit 28b8dc14c7
4 changed files with 32 additions and 17 deletions
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4
src/Ryujinx.Common/Helpers/Patterns.cs
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@ -9,6 +9,7 @@ namespace Ryujinx.Common.Helper
public static readonly Regex Numeric = NumericRegex(); public static readonly Regex Numeric = NumericRegex();
public static readonly Regex AmdGcn = AmdGcnRegex(); public static readonly Regex AmdGcn = AmdGcnRegex();
public static readonly Regex AmdRdna3 = AmdRdna3Regex();
public static readonly Regex NvidiaConsumerClass = NvidiaConsumerClassRegex(); public static readonly Regex NvidiaConsumerClass = NvidiaConsumerClassRegex();
public static readonly Regex DomainLp1Ns = DomainLp1NsRegex(); public static readonly Regex DomainLp1Ns = DomainLp1NsRegex();
@ -46,6 +47,9 @@ namespace Ryujinx.Common.Helper
"Radeon (((HD|R(5|7|9|X)) )?((M?[2-6]\\d{2}(\\D|$))|([7-8]\\d{3}(\\D|$))|Fury|Nano))|(Pro Duo)")] "Radeon (((HD|R(5|7|9|X)) )?((M?[2-6]\\d{2}(\\D|$))|([7-8]\\d{3}(\\D|$))|Fury|Nano))|(Pro Duo)")]
internal static partial Regex AmdGcnRegex(); internal static partial Regex AmdGcnRegex();
[GeneratedRegex("Radeon ([7-8](\\d{2}\\d?)[MS]|PRO [VW]7(\\d{2}\\d?)|RX 7\\d{3}([MS]?| XTX?| GRE)?)")]
public static partial Regex AmdRdna3Regex();
[GeneratedRegex("NVIDIA GeForce (R|G)?TX? (\\d{3}\\d?)M?")] [GeneratedRegex("NVIDIA GeForce (R|G)?TX? (\\d{3}\\d?)M?")]
internal static partial Regex NvidiaConsumerClassRegex(); internal static partial Regex NvidiaConsumerClassRegex();

4
src/Ryujinx.Graphics.Vulkan/PipelineBase.cs
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@ -1526,6 +1526,9 @@ namespace Ryujinx.Graphics.Vulkan
} }
private bool ChangeFeedbackLoop(FeedbackLoopAspects aspects) private bool ChangeFeedbackLoop(FeedbackLoopAspects aspects)
{
// AMD RDNA 3 GPUs only
if (Gd.IsAmdRdna3)
{ {
if (_feedbackLoop != aspects) if (_feedbackLoop != aspects)
{ {
@ -1542,6 +1545,7 @@ namespace Ryujinx.Graphics.Vulkan
return true; return true;
} }
}
return false; return false;
} }

2
src/Ryujinx.Graphics.Vulkan/PipelineDynamicState.cs
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@ -1,6 +1,7 @@
using Ryujinx.Common.Memory; using Ryujinx.Common.Memory;
using Silk.NET.Vulkan; using Silk.NET.Vulkan;
using Silk.NET.Vulkan.Extensions.EXT; using Silk.NET.Vulkan.Extensions.EXT;
using System;
namespace Ryujinx.Graphics.Vulkan namespace Ryujinx.Graphics.Vulkan
{ {
@ -27,6 +28,7 @@ namespace Ryujinx.Graphics.Vulkan
public uint ViewportsCount; public uint ViewportsCount;
public Array16<Viewport> Viewports; public Array16<Viewport> Viewports;
[Flags]
private enum DirtyFlags private enum DirtyFlags
{ {
None = 0, None = 0,

5
src/Ryujinx.Graphics.Vulkan/VulkanRenderer.cs
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@ -92,6 +92,7 @@ namespace Ryujinx.Graphics.Vulkan
internal bool IsAmdWindows { get; private set; } internal bool IsAmdWindows { get; private set; }
internal bool IsIntelWindows { get; private set; } internal bool IsIntelWindows { get; private set; }
internal bool IsAmdGcn { get; private set; } internal bool IsAmdGcn { get; private set; }
internal bool IsAmdRdna3 { get; private set; }
internal bool IsNvidiaPreTuring { get; private set; } internal bool IsNvidiaPreTuring { get; private set; }
internal bool IsIntelArc { get; private set; } internal bool IsIntelArc { get; private set; }
internal bool IsQualcommProprietary { get; private set; } internal bool IsQualcommProprietary { get; private set; }
@ -378,6 +379,10 @@ namespace Ryujinx.Graphics.Vulkan
IsAmdGcn = !IsMoltenVk && Vendor == Vendor.Amd && Patterns.AmdGcn.IsMatch(GpuRenderer); IsAmdGcn = !IsMoltenVk && Vendor == Vendor.Amd && Patterns.AmdGcn.IsMatch(GpuRenderer);
IsAmdRdna3 = Vendor == Vendor.Amd && (Patterns.AmdRdna3.IsMatch(GpuRenderer)
// ROG Ally (X) Device IDs
|| properties.DeviceID is 0x15BF or 0x15C8);
if (Vendor == Vendor.Nvidia) if (Vendor == Vendor.Nvidia)
{ {
Match match = Patterns.NvidiaConsumerClass.Match(GpuRenderer); Match match = Patterns.NvidiaConsumerClass.Match(GpuRenderer);